How to handle assertion disables in gate-level simulation?

How to handle assertion disables in gate-level simulation?

Повідомлення Williamhawk » 04 грудня 2017, 12:20

Hi,
I'm running into an issue re-using assertions in gate-level sims.
At the top level of our testbench, I have a number of control bits that are used as the disable conditions for our assertions. The problem is that in gate-level sim, all those signals are gone, presumably as they don't connect to the design.
Right now I'm working around the issue by defining a series of gate-sim specific behavioral tasks that uses $asserton and $assertoff to control assertions, but I have to write one statement for each and every assertion out there and it seems to me that there surely must be a better and cleaner way to do this.
Any recommendations on how one can go about controlling assertion disables that functions smoothly both in regular sim and gate-level sim?
Please help.
Thanks!
I didn't find the right solution from the Internet.
References:https://verificationacademy.com/forums/systemverilog/how-handle-assertion-disables-gate-level-simulation

Business Motion Graphics Example
Williamhawk
 
Повідомлень: 55
З нами з: 25 жовтня 2017, 07:09

Повернутись до Семінари

Хто зараз онлайн

Зараз переглядають цей форум: Немає зареєстрованих користувачів і 0 гостей

cron